A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine

A Posit Arithmetic Unit Enabled RISC-V Processor - Aneesh Raveendran & Vivian Desalphine, Centre for Development of Advanced Computing, Bangalore, India Posit arithmetic is popularly being discussed and analysed in research community about providing better accuracy and larger dynamic range than conventional IEEE 754-2008 based Floating point arithmetic. Such analysis has catalyzed the efforts in applying such new arithmetic for various applications domains viz. scientific, signal processing, AI/ML etc. This work presents a Posit Arithmetic Unit (P16, P32, P64, quire: parameterizable) enabled RISC-V processor (RV64IMAFD) architected with 6-stages in-order pipeline and FreeRTOS bootable. The RISC-V processor supports either IEEE 754-2008 FP or Posit (RISC-V F and D ISA based) arithmetic. The Posit unit has been verified with an in-house developed Posit domain specific verification suite, PositGen. RISC-V GCC software toolchain has been suitably enhanced to support Posit data representation in applications. Pos