Implementation of an Out-of-order RISC-V Vector Unit- Roger Espasa, SemiDynamics Technology Services

Implementation of an Out-of-order RISC-V Vector Unit - Roger Espasa, SemiDynamics Technology Services In this talk we will describe Semidynamics’ vector unit implementing the RVV-010 specification and we will focus on the challenges of supporting out-of-order execution for vector instructions. We will cover the challenges of renaming vector registers in the presence of LMUL, SEW, narrowing & widening and the different flavors of masking in the RV vector ISA. We will also provide an overview of the vector load/store pipeline. For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: