Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Ver... Simon Davidmann & Lee Moore

Lightning Talk: Open-Source RISC-V Cores with Industrial Strength Verification - Simon Davidmann & Lee Moore, Imperas Software This case study explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open-source IP core, the initial deliverable quality is not the only concern. One attractive aspect of an open-source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in to the testbench to accommodate future modifications as adopters extend the core features. For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: