Lightning Talk: How to Extend RISC-V to Accelerate AI/ML - Veronia Iskandar & Dr. William Jones

Lightning Talk: How to Extend RISC-V to Accelerate AI/ML - Veronia Iskandar, TU Dresden & Dr. William Jones, Embecosm We present the development of a simple ISA extension to the Open Hardware Group’s CV32E40P core, extending earlier work from the University of Southampton (). We have created a physical realization on the Nexys-A7 FPGA board under the 2021 Google Summer of Code program. We add a subset of just 8 instructions from the V extension to the Open Hardware Group CV32E0P core. The CV32E40P features an Auxiliary Processing Unit (APU) interface. This follows a subset of the OBI interface used to communicate with system memory. We use this interface for the accelerator. Several modifications were required to the core RTL in order to better support the architecture of the accelerator, primarily in regards to multi-cycle instructions. The accelerator and core RTL are then taken through the stages of FPGA development, starting from bitstream generation to debugging binary files