FastPI Using Standard PI Models to Expedite Platform PDN Design Optimization and Signoff

Presented at the Signal Integrity Journal Forum 2021, Kinger Cai, platform electrical architect from Intel, shares how PCB design cycles are accelerated with the FastPI streamlined platform power distribution network (PDN) design architecture. This architecture provides distributed computing on private or public clouds upon a standard power integrity model (SPIM) that includes scalable unified PI target (UPIT) and compact voltage regulator model (CVRM) models. With automated design optimization, review and signoff can be expedited to address multi-layer ceramic Intel customer TTM Technologies. Cost, performance, stackup, and physical dimension tradeoffs are enabled with a Cadence design and analysis framework featuring Cadence Allegro and Sigrity technologies on FastPI with Intel SPIM and CVRM products. Connect with Cadence: Website: YouTube: Facebook: LinkedIn: Twitter: About Cadence: Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design™ strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence® customers are the world’s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at .